Unit V: Memory Management

⭐Memory Protection

1. Introduction to Memory Protection

Definition: Memory protection is a feature of modern operating systems and processors that controls access to a system’s memory.
Purpose: Prevents one process from accessing or modifying another process's memory, enhancing security, stability, and error management.
How It Works: Uses mechanisms like base and bound registers, paging, and translation to isolate process memory and manage permissions.

2. Base and Bound Registers

Base Register:
- Holds the starting address of a process's memory space in physical memory.
- Ensures that a process only accesses memory within its allocated range.
Bound Register:
- Specifies the maximum limit or end address of a process's memory space.
- Any attempt to access memory beyond the bound register triggers a protection fault or error.
How They Work Together:
- When a process tries to access memory, the system checks if the address is between the base and bound registers.
- If within range: The memory access is allowed.
- If outside range: An error or exception is raised, preventing unauthorized access.

3. Page-Based Memory Systems

Paging:
- Divides memory into fixed-size blocks called pages (for virtual memory) and page frames (for physical memory).
- Each process has its own virtual address space, which is divided into pages.
Page Table:
- A data structure that maps each virtual page to a page frame in physical memory.
- Keeps track of where each virtual page is stored, facilitating address translation.
Advantages of Paging:
- Simplifies Memory Management: Allows processes to use a contiguous virtual address space, even if physical memory is fragmented.
- Memory Protection: Pages can be individually marked as read-only, read-write, or execute-only, preventing processes from accessing or modifying unauthorized pages.
Challenges:
- Overhead: Maintaining page tables for each process can use a significant amount of memory.
- Performance: Frequent address translations can slow down memory access.

4. Translation and Protection

Address Translation:
- Converts a process’s virtual address (used in its code) to a physical address in RAM.
- Allows processes to run in a "virtual" space, separate from the actual physical memory layout.
Protection Mechanisms in Translation:
- Each page in the page table can have protection bits (e.g., read, write, execute) that define access rights.
- The system checks these bits before allowing access to ensure the process has the correct permissions.
Protection Types:
- Read-Only: Allows processes to read data but not modify it.
- Read-Write: Allows processes to read and modify data.
- Execute-Only: Allows processes to execute code but not read or modify it.
Benefits:
- Prevents unauthorized access by enforcing restrictions on each memory segment.
- Provides isolation between processes, ensuring that one process does not affect another’s memory space.

5. TLB (Translation Lookaside Buffer) Processing

Definition: A small, fast cache in the CPU that stores recent virtual-to-physical address translations, speeding up memory access.
Purpose: Reduces the time it takes to translate virtual addresses to physical addresses by avoiding frequent page table lookups.
How TLB Works:
- When a process accesses a memory location, the CPU checks the TLB first for the address translation.
- If a match (TLB hit) is found, the CPU uses the translation directly, speeding up access.
- If no match (TLB miss) is found, the CPU consults the page table, updates the TLB with the new translation, and then accesses memory.
TLB and Memory Protection:
- TLB entries store not only the address translation but also the protection bits (read, write, execute) for each page.
- This allows the CPU to quickly check permissions before accessing memory, ensuring that all access rights are respected.
Benefits of TLB:
- Speeds Up Access: Reduces the overhead of frequent page table lookups.
- Improves System Performance: By caching recent translations, the TLB can significantly reduce the time needed for memory access in programs with high memory demand.
Limitations:
- TLB Size: The TLB has limited entries, so it may not store all required translations, especially for large programs.
- TLB Misses: When a translation is not in the TLB, accessing the page table can slow down the memory access time.

⭐Superscalar2 & Exception Handling

1. Interrupts

Definition: Interrupts are signals generated by hardware or software to interrupt the normal execution of a program and request the processor's attention to handle a specific event or condition.
Purpose: Interrupts allow the processor to respond to events in real-time, such as input/output (I/O) operations, system errors, or external hardware requests.
Types of Interrupts:
- Hardware Interrupts: Triggered by external hardware devices, such as keyboards, mice, or timers. Examples include an interrupt for a key press or a data ready signal from a disk.
- Software Interrupts: Generated by the software to invoke system services or perform specific operations (e.g., system calls). This is usually done via a special instruction in the code (like INT in x86 assembly).
- Maskable Interrupts: Interrupts that can be ignored or "masked" by the processor if certain conditions are met (e.g., disabling interrupts in critical sections).
- Non-Maskable Interrupts (NMI): Interrupts that cannot be disabled, typically used for critical events like hardware failures.
How Interrupts Work:
1. An interrupt occurs and is sent to the processor.
2. The processor suspends the current program execution.
3. It saves the current state (context), so the program can resume after the interrupt is handled.
4. The processor jumps to a special routine called an Interrupt Service Routine (ISR) to handle the interrupt.
5. After handling the interrupt, the processor restores the context and continues executing the interrupted program.

2. Exceptions

Definition: Exceptions are events that occur during the execution of a program, typically caused by errors or exceptional conditions that need special handling (e.g., divide by zero, invalid memory access, etc.).
Difference from Interrupts:
- Interrupts: Generated by external devices (hardware) or software.
- Exceptions: Generated by the processor itself during program execution due to certain conditions or errors.
Types of Exceptions:
- Traps: A type of exception that is intentionally generated by the program, typically to request a system service (e.g., a system call).
- Faults: Occur when an operation cannot be completed, but the processor can recover and continue execution (e.g., page faults where a page is not in memory).
- Aborts: Severe errors where recovery is not possible, and the process is typically terminated (e.g., hardware failures).
Handling Exceptions:
1. When an exception occurs, the processor halts the current instruction execution.
2. It saves the context (such as program counter) and transfers control to an exception handler.
3. After the exception is handled (e.g., by terminating the program, correcting the error, or loading a page), the processor resumes execution from the appropriate point.
Common Examples of Exceptions:
- Divide-by-zero exception: Occurs when a division by zero is attempted.
- Invalid memory access: Attempting to access memory that is not allocated or protected by the operating system.
- Segmentation fault: Happens when a program accesses memory outside its allocated address space.

3. Bypassing (Data Forwarding)

Definition: Bypassing (also known as data forwarding) is a technique used in out-of-order processors to handle data hazards by passing the results of one instruction directly to a subsequent instruction, without waiting for it to be written back to the register file.
Purpose: Reduces delays that would otherwise occur due to data dependencies between instructions (e.g., when an instruction needs the result of a previous instruction).
How Bypassing Works:
- When one instruction produces a result, that result is forwarded (or bypassed) directly to another instruction that needs it, instead of waiting for the first instruction to complete and update the register file.
- This allows subsequent instructions to execute more quickly, improving performance and throughput in the pipeline.
Example:
- Instruction 1: R1 = R2 + R3 (results in R1)
- Instruction 2: R4 = R1 + R5 (depends on R1)
- Without bypassing, Instruction 2 would have to wait for Instruction 1 to finish and update R1. With bypassing, the result from Instruction 1 can be forwarded directly to Instruction 2, allowing it to execute immediately.
Benefits:
- Reduces pipeline stalls and improves instruction throughput.
- Allows instructions that would normally be delayed due to data dependencies to execute in parallel.

4. Out-of-Order Processors

Definition: Out-of-order processors are CPUs that can execute instructions in a non-sequential order, based on the availability of execution units and data, rather than strictly following the order in which instructions appear in the program.
Purpose: To improve performance by exploiting instruction-level parallelism and utilizing CPU resources more effectively.
How Out-of-Order Execution Works:
- Instruction Fetch: Instructions are fetched in order from memory.
- Instruction Decode: Instructions are decoded, but execution is delayed based on the availability of operands.
- Reordering: Instructions that do not have dependencies (e.g., no data hazards) can be executed as soon as their required resources (like execution units) are available, regardless of their position in the program.
- Reordering Buffer: Instructions are stored in a reorder buffer, and once completed, they are committed (written back) in the original program order.
Pipeline Stages:
- Dispatch: Instructions are dispatched to different functional units based on their requirements.
- Execute: Instructions are executed out of order, with results being forwarded if necessary.
- Commit: Once an instruction completes execution, it is committed in program order (to avoid corruption of the state).
Benefits:
- Increased throughput: Instructions are processed as soon as possible, utilizing idle CPU resources.
- Improved performance: Reduces the impact of pipeline hazards like data dependencies and memory latency.
Challenges:
- Complexity: Out-of-order execution requires sophisticated hardware to track instruction dependencies, manage instruction reordering, and handle exceptions correctly.
- Dependency Checking: The processor must carefully check for dependencies between instructions to ensure correctness.
Examples of Out-of-Order Processors:
- Superscalar Processors: These processors can issue multiple instructions per clock cycle and execute them out of order.
- Dynamic Scheduling: Hardware mechanisms like Tomasulo's algorithm and register renaming are used in out-of-order processors to ensure that instructions are executed efficiently without violating dependencies.

⭐Superscalar3: Advanced Superscalar Architectures

1. I2O2, I2O1, IO3, IO2I Processor Architectures

I2O2 Processor (Instruction-Level Parallelism):
- I2O2 stands for Instruction-to-Instruction execution model, where the processor can execute two instructions in parallel per cycle.
- This model is a type of superscalar architecture that allows the simultaneous execution of two independent instructions in each pipeline stage.
I2O1 Processor:
- The I2O1 architecture allows the processor to execute one instruction per cycle but with the ability to issue multiple instructions in parallel (multi-issue architecture).
- It focuses on optimizing instruction fetching and decoding to allow higher throughput without increasing the number of execution units dramatically.
IO3 Processor (Input-Output Parallelism):
- IO3 refers to processors capable of executing three instructions per clock cycle in parallel.
- This type of architecture allows for greater instruction-level parallelism (ILP), with specialized hardware capable of handling three instruction streams simultaneously.
- Characteristics: Requires a complex pipeline with more functional units and execution resources.
IO2I Processor (Input-Output Parallelism with Instruction-level Parallelism):
- IO2I is an advanced processor architecture combining input/output operations and instruction-level parallelism.
- In this architecture, two instructions are executed in parallel in the processor's execution units, while also being capable of managing I/O operations alongside computation.
- It provides high throughput for workloads involving both computation and heavy I/O tasks, such as multimedia processing.

2. Superscalar4

Definition: A Superscalar4 processor refers to a processor architecture capable of issuing four instructions per clock cycle, hence increasing the degree of instruction-level parallelism (ILP).
How Superscalar4 Works:
- The processor has four execution units (ALUs, FPUs, Load/Store units), and it can dispatch up to four instructions simultaneously.
- Multiple pipelines: Multiple pipelines allow different types of instructions to be executed in parallel, such as integer operations, floating-point operations, and memory accesses.
Challenges:
- Complexity: Managing four instructions per cycle requires sophisticated scheduling, out-of-order execution, and interlocking mechanisms to handle data dependencies and hazards.
- Pipeline stalls: More instruction slots per cycle may lead to stalls if instructions have interdependencies or require the same resources.
Benefits:
- Higher performance for applications that can exploit multiple parallel instruction streams.
- Better resource utilization by keeping multiple execution units active.

3. VLIW (Very Long Instruction Word) Architectures

VLIW1 (First-generation VLIW):
- Definition: VLIW1 refers to a VLIW architecture that packs multiple operations into a single long instruction word. Each instruction word typically contains several independent operations that can be executed in parallel.
- How It Works: In VLIW, instructions are grouped together and encoded in a very long instruction word (e.g., multiple ALU operations, load/store, and branches within one instruction).
- Instruction Format: The processor decodes these long instruction words, and each operation is executed in parallel by the corresponding execution unit.
- Characteristics:
  - Compiler-Driven: The compiler decides which operations to group together, thus relieving the processor from dynamic scheduling.
  - Parallelism: Exploits multiple execution units to perform several operations in parallel without the need for complex hardware-based scheduling logic.
  - Limited Dynamic Scheduling: Since operations are grouped statically, dynamic scheduling is limited, and the performance gain depends on the effectiveness of the compiler.
Challenges:
- Compiler Dependency: The performance of VLIW heavily relies on the compiler's ability to schedule independent instructions and efficiently utilize the available execution units.
- Code Size: The long instruction words can lead to larger code sizes, especially for programs that cannot fully utilize parallelism.
Benefits:
- Simplicity: Simplifies the hardware design by avoiding the need for complex dynamic scheduling mechanisms.
- Efficiency: When the compiler can schedule instructions effectively, VLIW can achieve high performance by using available resources optimally.

VLIW2 (Second-generation VLIW):
- Definition: VLIW2 is an enhanced version of the original VLIW architecture that introduces more flexible and efficient ways to encode instructions and handle parallelism.
- Improvements over VLIW1:
  - More Execution Units: VLIW2 supports more execution units per instruction cycle, which means it can perform more parallel operations.
  - Enhanced Instruction Encoding: VLIW2 can handle more sophisticated instruction encoding schemes, allowing greater flexibility in how parallel operations are packed.
  - Better Handling of Branches: VLIW2 may introduce mechanisms for better branch handling and prediction, improving performance when there are branching instructions within long instruction words.
Advantages over VLIW1:
- Better Parallelism: VLIW2 can pack more operations into each instruction word, which leads to better utilization of available execution resources.
- Reduced Code Size: With better instruction encoding and handling, VLIW2 can reduce the overhead of long instruction words compared to VLIW1.
Challenges:
- Still Compiler-Dependent: Like VLIW1, VLIW2 relies heavily on the compiler to schedule independent instructions, which can limit its effectiveness if the compiler is not optimized.
- Complexity in Hardware: Even though VLIW2 reduces some issues, it may still require complex hardware to decode and execute long instruction words efficiently.

4. Branch Prediction

Definition: Branch prediction is a technique used in modern processors to guess the direction of a branch instruction (whether it will be taken or not) before the actual condition is evaluated. This helps to avoid pipeline stalls caused by branch instructions, thereby improving performance.
Types of Branch Prediction:
- Static Prediction:
  - Always Taken: Assumes branches are always taken (often used in early processors).
  - Always Not Taken: Assumes branches are never taken.
  - These methods are simple but generally inaccurate compared to dynamic prediction techniques.
- Dynamic Prediction:
  - Bimodal Prediction: Uses a simple table (usually a 2-bit counter) to predict the branch outcome. It keeps track of the last outcome of a branch to predict future behavior.
  - Two-Level Adaptive Predictors: Use more sophisticated algorithms that take into account the history of branches and their outcomes to make more accurate predictions.
  - Branch History Table (BHT): Stores past branch behavior, improving prediction accuracy for loops and frequently executed branches.
How Branch Prediction Works:
- The processor predicts whether a branch will be taken or not before it reaches the branch instruction.
- If the prediction is correct, the processor continues fetching and executing subsequent instructions without delay.
- If the prediction is wrong, the pipeline is flushed, and the correct instructions are fetched, causing a penalty in performance but allowing the processor to recover.
Benefits:
- Reduced Pipeline Stalls: By predicting branches, the processor can continue fetching instructions without waiting for the branch decision, which improves the instruction throughput.
- Better Utilization of Resources: More instructions can be fetched and executed in parallel, improving overall performance.
Challenges:
- Prediction Accuracy: Branch prediction accuracy is critical—poor predictions lead to pipeline flushes and performance penalties.
- Hardware Complexity: Implementing accurate branch predictors increases processor complexity and requires additional hardware resources.

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Unit V: Memory Management | CSE211: COMPUTER ORGANIZATION AND DESIGN | B.Tech CSE